Application-Specific Multi-Processor SoC
Summer school sponsored by IEEE Circuits and Systems Society and EDAA
9 - 13 July 2001, Aix-les-Bains, France

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9th July
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13th July
  Session 2: 
Multi-processor SOC

Building Systems on a Chip with Trimedia technology
K. Vissers, TriMedia Technologies

From Applications to Multi-Processor DSP Architectures 
P. Pirsch, U. Hannover

Energy-efficient design and management of SoCs 
G. De Micheli, Stanford U.

Session 4: 
RTOS for Embedded Systems

From a distributed embedded RTOS to a pragmatic framework for multi-core SoC
E. Verhulst, Eonic Solutions

Task-level run-time scheduling approach
for dynamic multi-
media systems
F. Catthoor, IMEC

Modeling real-time 
J. Sifakis, Verimag

Session 6: 
Embedded RT-SW

Challenges in Network Processor Architec-tures and Embedded S/W Tools
P. Paulin, STMicroelectronics

Challenges in Network Processor Architec-tures and Embedded S/W Tools
F. Karim, STMicroelectronics

Adaptive EPIC Processors and Com-pilation Techniques
K. Palem, Georgia Tech

Session 8: System-Level Architecture

Communication architectures for deep-submicron VLSI Systems 
J. van Meerbergen, Philips

System Architectures: Hardware or Software dominant ? A Case Study: xDSL modems
M. Genoe, Alcatel

Architecture and Implementation of Application-Specific Multi-processor SOCs for Digital TV (DTV) and Media-Processing Applications
S. Dutta, Philips

Testing Future System-on-Chips: Challenges and Emerging Techniques
S. Dey, U. California, San Diego

Session 1: Embedded System Specification

Specification and Validation for Heterogeneous Multi-processor SoC 
A. Jerraya, TIMA

Platform based design of embedded systems-on-chip 
W. Rosenstiel, U. Tuebingen & FZI

Session 3:
RTOS for Embedded Systems

Real-Time Operating Systems: Principles 
and a Case Study
K. Shin, U. Michigan

RTOS for Embedded Systems and SoC
M. Potkonjak, UCLA

Real-Time Inter-Pro-cessor Synchronization Algorithms 
H. Takada, Toyohashi U. of Technology

Session 5: System-Level Architecture

The Architecture of Multiprocessor Systems on a Chip
T. Mudge, U. Michigan

SOC Multiprocessor Architecture and Modeling
R. Ernst, TU Braunschweig

Architectural challenges and oppor-tunities for systems on a chip
B. Rau, Hewlett-Packard

Session 7:
Embedded RT-SW

Multiprocessor SoCs for Video Processing
W. Wolf, Princeton U.

Configuring the Jazz VLIW-DSP Core for Application Specific Requirements
O. Levia, Improv Systems

Static scheduling for embedded systems 
L. Lavagno, U. Udine

Session 9: 
SoC Validation and Test

System on Chip: Embedded Test Strategies 
Y. Zorian, LogicVision