Networks on a chip: a new paradigm for System on Chip designLECTURES
Giovanni De Micheli, Stanford University, USA
We consider systems on chips (SoCs) that will be designed and produced with silicon technologies scaled down to the [25-75] nm range. We address the distinguishing features of a design methodology that aims at achieving reliable designs under the limitations of the interconnect technology. Specifically, we consider the trade-off among performance, energy consumption reduction and reliability as a main objective in system design.
We show that the unreliability of the physical layer is a potential show-stopper for SoC design. We argue that network technology can be used to provide a framework for designing on-chip interconnect. We visit different layers of a micro-network stack abstraction and show new directions toward designing on-chip communication.
SoC Architecture for HW Designers
Trevor Mudge, Bredt Professor of Engineering, Dept. EECS, Univ. Michigan, USA
This tutorial will start with an examination of the typical components found in a system-on-a-chip (SoC). We will then show how these can be assembled to form a platform that targets a particular application domain. The emphasis will be on bus based systems. Case studies of existing platforms will be given. Current design challenges will be discussed including: system wide power regulation; multiple clock domains; integrated memory; mask and manufacturing costs; and power/performance modeling. The tutorial will conclude with a brief discussion of software, in particular the impact of the hardware design decisions on programmability.
Hardware dependent Software (HdS) for Multiprocessor SoCs. An introduction.
Frank Pospiech, Alcatel HQ HW Coord., HdS Program Manager, Belgium
Given the increasing complexity of modern SoCs, mastering of the software related issues becomes more and more important. The concept of Hardware dependent Software (HdS) has been introduced in order to deal with the hardware-software interface in an efficient way, and to allow to de-couple HW and SW design and re-use issues as much as possible.
Modern Multiprocessor SoC architectures pose special requirements on HdS, e.g. in terms of distributed boot and bring-up, and for supporting the complex communication insides and outsides an MPSoC. This presentation introduces the concept of Hardware dependent Software, and discusses some aspects of HdS design for MPSoCs. The status of some HdS related standardization efforts is briefly described.
Network on Chip
Designing advanced NoCs architectures
Luca Benini, DEIS, Universita' di Bologna, Italy
Networks on chip (NoCs) are emerging as the next-generation communication infrastructure for MPSoC. As research and development matures, many NoC embodiments are being proposed and investigated in details. This presentation gives an overview of various NoC design efforts, comparing and contrasting design targets and implementation choices. The analysis will be mainly focused on architectural and system-level issues, but critical implications at lower abstraction levels will also be considered.
Systems on Chip and Networks on chip: bridging the gap with QoS
Kees Goossens, Embedded Systems Architectures on Silicon (ESAS) group, Philips Research, The Netherlands
In this talk I will explain the need for Quality of Service (QoS) for chips and networks on chip (NoC) in consumer electronics. The tension between the need for local, composable subsystems and global predictability (i.e. QoS) will be explained. This gives a rationale for Philips's Aethereal NoC. I will describe the various QoS properties used to balance the required levels of predictability with the associated costs, with some architectural insights of the Aethereal NoC.
Communication Refinement for a Network-on-Chip Platform
Axel Jantsch, KTH, Sweden
A Network-on-Chip (NoC) is determined by the communication infrastructure and by the communication services it provides. The communication services are hierarchically defined in terms of a protocol stack where higher level services are mapped onto lower level services. Applications are modeled as a set of communicating processes using high level communication and synchronization operations such as send/receive with defined priority and guaranteed bandwidth.
In this talk we will present a set of application level communication primitives, a NoC communication service infrastructure in terms of a protocol stack and a refinement strategy to map the former onto the latter. We will illustrate this procedure for both a software and a hardware resource in the NoC.
SoC-Network for Interleaving in Wireless Communications
Norbert Wehn, University of Kaiserslautern, Germany
Interleaving is an important step on the physical layer in communication systems. It is used to minimize burst errors. Interleaving scrambles the data processing order to yield timing diversity. Sophisticated channel coding schemes like Turbo- or LDPC Codes heavily rely on it. The interleaving process represents the bottleneck in high throughput architectures. In this talk we will present a scalable communication network for interleaving in highly parallel architectures. An application-specific multiprocessor system is presented composed of Tensilica cores. These cores are optimized with respect to the application and connected via this communication network.
OCCN: an environment for NoC exploration
Marcello Coppola, STM, Grenoble AST lab manager, France
The On-Chip Communication Network (OCCN) proposes an efficient research and development framework for the specification, modeling and simulation of NoC. OCCN increases the productivity of developing new models for NoC through the definition of a universal Application Programming Interface (API) and an object-oriented C++ library built on top of SystemC.
Moreover, OCCN enables reuse of executable models across a variety of SystemC-based environments and simulation platforms, and addresses various design exploration, model portability, simulation platform independence, interoperability, and high-level performance modeling issues.
Reconfigurable Systems-on-Chip for wireless multimedia terminals: will it become of industrial relevance or will it stay an academic curiosity?
Rudy Lauwereins, IMEC & KU Leuven, Belgium
We often hear the world is evolving towards ambient intelligence where mobile terminals can exchange multimedia information at any time and any place. Is ambient intelligence another buzzword like artificial intelligence with which it shares the abbreviation AI? What are the properties of ambient intelligence? What will be needed from a technological point of view? Electronic terminals in an ambient intelligent environment should combine power efficiency with run-time flexibility. These are conflicting requirements. Re-configurable devices are presented by academia as the solution, but is it also economically relevant and viable? How reconfigurable should the terminal be at the multimedia application level and at the wireless communication level? Should the RF part become reconfigurable too and is that technically feasible?
StepNP: A Driver for Multi-processor SoC tools
Pierre Paulin, Director - SoC Platform Automation, STMicroelectronics, Central R&D, Ottawa, CANADA
This talk addresses challenges in the analysis, debug and programming of parallel network processors. In order to explore the issues with modern-day network processors, we have developed a highly configurable platform for network processors, dubbed StepNP.
After a quick overview of StepNP, we focus on the experimental MultiFlex SoC tool environment used to program and analyze parallel applications running on the platform. We will discuss the transaction-level modelling approach in SystemC, the model interaction with external tools, the parallel programming model, and the multi-processor compilation approach.
We will demonstrate results for an 10 Gbit/sec IPv4 packet processing application.
Design-Space Construction and Exploration
Janos Sztipanovits, Director of Institute for Software Integrated Systems, Vanderbilt University, USA
A fundamental requirement for achieving rapid turn-round and short time-to-market in embedded software and system development is to achieve high level of reuse. Model-integrated computing offers a systematic way to make tradeoff between the conflicting requirements of flexibility and reuse. This talk presents a model-integrated approach in controlling and exploiting flexibility via the disciplined construction and automated exploration of large design-spaces on hardware/software platforms.
Physical/Virtual Co-Execution for HW/SW Co-Verification
Elliot Mednick, Cadence Design Systems, USA
Neither software-only nor hardware-only functional verification of SoCs is entirely satisfactory, especially when multiple processors are involved. HW/SW co-verification demands enough speed to execute OS and application code on the HW design in interactive time. Software-based (virtual) methods can lack speed and/or accuracy, while hardware (physical) can be inflexible and hard to debug with. It is possible to combine the best qualities of each in physical/virtual co-execution. A general-purpose co-verification protocol has been defined to connect physical and virtual verification elements, with accuracy, flexibility and good performance.
Reconfigurable EPGA's Bridging Worlds
Yankin Tanurhan, Applications and IP Solutions Group, Actel Corporation, USA
Reconfigurable systems in terms of computer architectures
Kees A. Vissers, UC Berkeley, USA
The purpose of this talk is to give an overview of the field and show that great progress has been made in reconfigurable computing. However we are only at the beginning of a very interesting area of multi-processor systems. Current silicon technology allows the integration of several hundreds of ALUs. Historically multi-processor systems have failed to make a significant industrial impact. However in the domain of embedded systems many ad-hoc multiprocessor systems have emerged. Unfortunately these have often been programmed in verilog or other dedicated, non-standard, specific
environments, with often very architecture specific choices in the configuration or program. The absence of a memory model makes the data and configuration routing explicitly visible. I will illustrate promising work that alleviates this problem, by introducing an explicit mapping step. The mapping can be static (compile time) or dynamic (run time). I will show the pros and cons of several approaches, and will put my contribution over the last 20 years in this field into perspective.
Reconfigurable Computing for System on a Chip
Hiroto Yasuura, Graduate School of Information science and Electrical Engineering, Kyushu University, Japan
Reconfigurable computing is a key technology for reducing cost and power consumption of SoC. Reconfigurable computing is also effective to improve reliability and security of SoC. Dynamic profiling, dynamic optimization and dynamic reconfiguration are important technologies. We discuss economical advantage of reconfigurable computing, new services of consumer products with reconfigurability and SoC design techniques.
SoC Design Methodologies
Energy-Aware Systems Design
Mary Jane Irwin, CSE and EE, Penn State University, USA
With no or little new technological miracle solutions on the horizon for solving the looming power/energy crisis, radical new design approaches and accompanying design methodologies/tools are a necessity. Just as with performance optimization, power optimization requires careful design at several abstraction levels - from innovative circuit fabrics, to the energy-aware micro-architectures that exploit them, to the software that runs on them - and careful consideration of the interactions across those levels.
This talk will address ways to improve energy efficiency across the design hierarchy - both active and standby - including circuit level optimizations such as supply and threshold voltage scaling, microarchitecture optimizations such as multiple supply voltages and sleep modes, and the interplay of various compiler and run-time system optimizations with the energy-aware micro-architecture features.
Multi-processor platform modeling in Metropolis
Luciano Lavagno, Politecnico di Torino, Italy
Metropolis is a specification, modeling, verification and synthesis framework for electronic systems. It is based on the principle of orthogonalization of concerns, in order to maximize re-use and verifiability, while keeping optimization as a primary objective. Design objects represent computation, communication, resources, and constraints (both functional and non-functional). Design is an activity based on refinement, de-composition, composition and analysis steps, supporting both top-down and bottom-up flows.
In this presentation we will cover both the basic of the design philosophy and the modeling language used in Metropolis (the Metropolis Meta-Model), using a realistic example including multiple processors and other computation and communication resources.
Modelling of Systems-on-Chip in SystemC
Wolfgang Rosenstiel, University of Tuebingen & FZI, Germany
The main message in the area of design in the 2001 International Technology Roadmap for Semiconductors (ITRS) is that “cost of design is the greatest threat to the continuation of the semiconductor roadmap”. This recent revision of the ITRS describes the major productivity improvements of the last few years as “small block reuse”, “large block reuse”, and “IC implementation tools”. In order to continue to reduce design cost, the required future solutions will be “intelligent test benches” and “embedded system-level methodology”. As the new system-level specification and design language, SystemC directly contributes to these two solutions. These will have the biggest impact on future design technology and will reduce system implementation cost.
In this context, it took SystemC as a combined hardware/software description language only two years to gain sufficient momentum and to get widely accepted by many users and tool vendors as the next generation system description language for that purpose. SystemC is currently controlled by an independent standardization body, the Open SystemC Initiative (OSCI), which is backed by a growing community of currently over 70 charter member companies from the systems, semiconductor, IP, embedded software, and EDA industries.
SystemC has successfully consolidated the design flow in use at many firms for some time, and standardized it by making available corresponding libraries. In this respect, SystemC follows the principle of defining a language not only by its syntax and semantics, but also by specification of various libraries. This principle was very successfully introduced by the Java language.
For more information, please visit http://www-ti.informatik.uni-tuebingen.de/~systemc. A good introduction into SystemC is the book from T. Grötker, S. Liao, G. Martin, S. Swan: System Design with SystemC, Kluwer, 2002
Embedding analog/RF blocks in Systems on Chip
Georges Gielen, KU Leuven, Belgium
Embedded Real-Time Operating Systems
HW-SW Interfaces Design for Multiprocessor SoC
Ahmed Jerraya, TIMA Laboratory, France
A multiprocessor on SoC is composed of four kinds of components: software tasks, processors executing software, specific hardware cores and a global on-chip communication network. The crucial issue when designing SoC is to include hardware and software elements that adapt these components to each other. Multiprocessor SoC are quite different from classic symmetrical multiprocessor architectures. This is mainly because the implementation of system communication is much more complicated since heterogeneous processors are involved and complex protocols and topologies are used for communication. This talk explores HW-SW interface models to adapt HW and SW components to on-chip communication network.
RTOS Modelling for Multi-Processor SoC using SystemC
Jan Madsen, Informatics and Mathematical Modelling, Technical University of Denmark
A multi-task system specification exhibits significant non-determinism, as only a partial ordering is specified. The behavior in terms of produced output, will be the same regardless of internal behavior or implementation details. However, the actual ordering and choice of implementation may influence a number of other parameters such as performance, power consumption, flexibility, reliability, production cost, etc. These parameters have to be captured and explored in order to produce a successful SoC design.
In this lecture we will focus on the task scheduling problem. We will use SystemC to introduce abstract RTOS modelling based on classical real-time scheduling for uni-processor systems. These are then extended to handle data dependencies, shared resources, context switching, and power reduction, which are all relevant for SOC. Finally, we will extend the model to handle the problem of multi-processor scheduling.
Energy-Aware Quality of Service Adaptation
Kang G. Shin, Real-Time Computing Laboratory, Dept. of Electrical Engineering and Computer Science, The University of Michigan, USA
In a wide variety of embedded control applications, it is often the energy resources that form the fundamental limits on the system, not the system's computing capacity. Various techniques have been developed to improve energy efficiency in hardware, such as Dynamic Voltage Scaling (DVS), effectively extending the battery life of these systems. However, a comprehensive mechanism of task adaptation is needed in order to make the best use of the available energy resources, even in the presence of DVS or other power-reducing mechanisms. Further complicating this are the strict timeliness guarantees required by real-time applications commonly found in embedded systems.
We have developed a new framework called Energy-aware Quality of Service (EQoS) that can manage real-time tasks and adapt their execution to maximize the benefits of their computation for a limited energy budget. The concept of an adaptive real-time task and the notion of utility, a measure of the benefit or value gained from their execution, are introduced. Optimal algorithms and heuristics are developed to maximize the utility of the system for a desired system runtime and a given energy budget, and then extended to optimize utility without regard to runtime. We demonstrate the effects of DVS on this system and how EQoS in conjunction with DVS can provide significant gains in utility for fixed energy budgets. Finally, we evaluate this framework through both simulations and experimentation on a working implementation.
This is joint work with Babu Pillai and Hai Huang.
MPSOC Architecture Modeling
Rolf Ernst, TU Braunschweig, Germany
An MPSOC typically consists of several different processors, co-processors, peripheral units, and memories which are connected by a complex communication infrastructure. These components are for the most part reused and provided by different sources, thereby shifting the design focus from traditional component development to a communication centric integration task. Integration is not limited to hardware but includes the basic software layers which are provided together with programmable components, such as drivers, run-time systems and application APIs. Global control and data flow verification and optimization become central issues in MPSOC design as different scheduling strategies, communication behaviors and performance requirements must be matched and combined on a single system.
This presentation will review novel approaches to model, analyze and even optimize the global MPSOC behavior.
ARM Multiprocessor Architecture
John Goodacre, ARM, U.K.
The ARM core, AMBA bus and PrimeCell peripherals have been used within multiprocessor SoC designs for some time. Last year ARM announced the PrimeXsys Dual Core Platform which for the first time exposed system-level components to explicitly support MPSoC. Since then, ARM has been working to formalize an architectural approach for both homogeneous, heterogeneous, symmetric and asymmetric designs. This talk will introduce how ARM is approaching the creation of an unified architecture for MPSoC and will discuss the details of multicore trace and debug, interprocessor communication, a mechanism of interrupt distribution and the model for memory coherence and consistency.
Fundamental Change in MPSOC: A fifteen year outlook
Chris Rowen, CEO, Tensilica, Inc., USA
The continued quantitative progress in semiconductor device scaling implies a profound qualitative shift in the design and structure of system-on-chip (SOC) devices.. A simple technology model, derived from the ITRS consensus view of semiconductor scaling, shows a series of fundamental transitions in SOC design, especially a fundamental change in the role of processors. Automatic generation of application-specific processors will allow processor cores to span many more roles in the SOC architecture, from high-performance control to data-intensive tasks previously realizable only with inflexible hard-wired logic. Large increases in intrinsic and extractable system-level parallelism will make the application-specific processor the basic building block of advanced SOCs. This model of processor scaling predicts that within fifteen years, single-chip designs with thousands of fully featured processors will be common and designs with hundreds of processors will be ubiquitous. This model also predicts that MPSOC computing performance will grow at 65% per year. Processors, including application-specific extensions, will dominate chip area devoted to logic, and processor RAM will dominate chip area devoted to memory. The central SOC design challenge will shift from isolated design of the subsystems, processors, and logic blocks to the rapid and reliable integration of software-rich subsystems into complete hardware/software systems. New interfaces will dramatically expand the interprocessor bandwidth available to architects, and new tools will provide an intuitive hardware/software cockpit in which all key chip-level hardware and software partitioning, optimization, design and verification tasks are performed in unified fashion.
Architectures for Embedded Video
Wayne Wolf, Princeton University & MediaWorks Technology, USA
Smart cameras perform real-time video analysis. Smart cameras may be single units or may be used in networks of cameras. High performance processors are required to meet the real-time requirements of smart cameras. This talk will describe issues in the design of MPSoCs for smart cameras and networks of smart cameras.
SoC Validation & Test
Functional Verification and the SoC Challenge
Avi Ziv, IBM Research Lab, Israel
Functional verification is widely acknowledged as the bottleneck of the hardware design cycle. In current designs, up to 70% of the design development time and resources are spent on functional verification. The design of systems on chips (SoCs) is based on use of processors and other black-box IP and close integration between the hardware and software of the system. This raises new challenges for the functional verification of SoCs and makes it even more difficult than verification of other complex ASICs. In this talk, we will present the main challenges of functional verification of SoCs, and describe some of the leading techniques and methodologies that are used for functional verification of complex chips. Then, we will discuss how these functional verification techniques can be used in SoC verification and what holes need to be filled to make functional verification of SoCs more efficient.
Challenges for the Next Decade
Andrea Cuomo, Corporate Vice President and General Manager, Advanced System Technology, STMicroelectronics, Italy
Semiconductors will play a key role to drive the technological evolution in the next 20 years. We already possess many of the technologies that will deeply change our scenario, among which we can mention nanotechnologies, bioelectronics, photonics…
The central role of Integrated Circuits in the economy will grow stronger and stronger in future, starting from the convergence between storage, security, video, audio, mobility and connectivity.
Systems are converging and ICs are more and more converging with systems. The fundamental issue is how to translate knowledge and competences coming from different fields into single architectures. This consideration implies two main challenges for our industry. The first challenge is to master a broad range of hardware and software technologies. The second, is to bring them into a single piece of silicon.
To win in this scenario, we must possess a broad IP portfolio and system know-how. Then, we need to have a large network of business and research partners, and to build key knowledge with them. We must also build the ability to pick up and integrate the innovative elements developed around the world. And in the end, a world-class manufacturing machine must translate all of this into world- class products, ensuring that customers receive the right device at the right time, in the right quantities, at the right price.
The key factor is to build the right culture. One one side, this implies to be open to share work, results and benefits with our research and business partners. On the other side, it means to build an organization for innovation, with the right mix of creativity, personal initiative and execution skills.
A Roadmap to 65nm for EDA
Raul Camposano, Sr. VP, CTO, Synopsys, USA
As we move to smaller technology nodes, the design of integrated circuits is undergoing profound changes. These changes arise mainly from three sources: business disruptions, increasing complexity, and manufacturing physics. This talk examines the technical challenges of complexity and manufacturing physics that design technology, and therefore EDA, face to effectively support the 65nm technology node.
The number of devices on a chip continues to increase exponentially in a fairly predictable manner following Moore’s law, certainly up to and including 65nm designs, although some may argue with a somewhat decreased speed. In addition, there is an explosive upsurge in the number of vectors needed to simulate for functional verification. Design and EDA have responded to these challenges by taking advantage of the following:
• Increasing memory size and speed of computers
• New and more effective algorithms used in the tools
• Improved Design Methodology
• An increased use of IP
• Higher levels of abstraction
• Larger design teams
Additionally, the physics of manufacturing at these smaller geometries is generating parasitic effects that must to be dealt with during design. Again, the issues are myriad:
• Increased parasitics and signal integrity effects
• “Design for manufacturing”
o More complex design rules• Packaging and test issues in EDA
o Resolution enhancement techniques for mask making
o Yield and statistical variations of critical dimensions
These issues are rapidly moving to the foreground of concern for the EDA industry. This presentation showcases the efforts that EDA vendors are putting forth to meet the advanced and ever-advancing needs of IC design.
New electronic frontiers, a System house point of view
Bernard Candaele, Head SoC & EDA Department, Thales, France
The semiconductor devices are major drivers for the electronic and IT industry. The IC complexity has increased from ASIC solutions to SoC platforms, whereas the vertical design teams have moved to multi-disciplinary development teams.
The concept of Software driven electronics has allowed fast changes of products by software updates on a platform based hardware. It requires to manage the overall performances of a combined SW-HW solution and to define a layered system approach (API).
This talk presents the new challenges for a system house :
- Management of the overall IT solution taking into account : end-user usage, quality of service, infrastructure and consumer products.
- Engineering process to manage the new manufacturing model of products. Innovation related organisation
- Process for system engineering : component approach for Software, HW related software, System level design
- SoC approach to address early time to market
- IC solutions to appear in the gap between the nanometer SoC at 100 Million unit/year and the Fpga
- Technology selection process. Market driven issues.
The presentation will outline the requirements for the related EDA solutions.