Opening Keynote: Digital Media – The New Frontier for Supercomputing
Lisa Su, VP, Technology Development and Alliances, IBM Systems and Technology Group, Hopewell Junction NY, USA
Mention a supercomputer and most people would visualize a room full of specialized computer equipment. The insatiable appetite of the video game developer community for photo realistic graphics and real time network interaction requires tremendous computing power and is driving the effort to develop a supercomputer on a chip. Advancements in semiconductor process technology such as silicon-on-insulator (SOI) technology, strained silicon techniques and low dielectric constant materials coupled with architectural enhancements such as multi-core microprocessors, high speed broadband I/O and memory, and floating point processing power bring supercomputer performance to consumer applications. These advances will change the look and feel of digital media applications in the future and will enable a platform for continued innovation.

Reliability and design of SoCs for reliability
Giovanni De Micheli, EPFL, Switzerland
Whereas research and development on reliable systems has permeated the last three decades, a renewed interest on single-chip reliability has been fueled by the technological progress, namely by the extremely small nature of electronic devices, the extremely large complexity of systems, and the new, uncharted territory set by nanotechnologies. This tutorial will review the basic models of semiconductor failures as well as the theory an practice of reliable system design. We will focus on physical and mathematical modeling, as well as on computational methods to asses reliability.

Configurable Core Generation for Multi-Processor SoC
Masaharu Imai, Graduate School of Information Science and Technology, Osaka University, Suita, Japan
This talk describes the state-of-the-art technology of the configurable processor core generation. First, the role of configurable processor core in the future MPSoC is described. Then the requirements to these processor cores are analyzed. Next, the generation technologies of configurable processor core and of application software development tools, including compiler, assembler, and ISS, are introduced. Finally, case studies of application domain specific processors based on configurable processor cores are shown.

On-Chip Interconnects: Circuits and Signaling from an MPSOC Perspective
Wayne Burleson, ECE Dept., University of Massachusetts Amherst, USA
This talk presents recent work in interconnect circuit modeling below 90nm CMOS emphasizing estimators for delay and power while accounting for noise and variations. Several new circuit and signaling techniques are presented which show improved speed and both dynamic and static power consumption while retaining robust behavior even in the presence of deep sub-micron effects. This talk has been groomed for the MPSOC audience to allow careful abstraction of interconnect issues thus allowing system-level design of global interconnects, buses and networks on chip, while also exposing several promising future directions.

Global Networking versus Networking-on-Chip
Martina Zitterbart, Institute of Telematics, University of Karlsruhe (TH) Germany

NoCs: pushing toward the back-end
Luca Benini, DEIS, University of Bologna, Italy 
Network-on-chips are gaining momentum as the interonnection fabric for fabric of choice for future MPSoCs. Architectural scalability trends and  design technology arguments are favorable to the NoC approach, but designers want hard facts and they need solutions that do not require disruptive changes in design technology.  In this talk we will look into the experience and lessons learned in developing a complete back-end flow for NoC deployment in current real-life silicon technology.

From spaghetti wires to NoC
Marcello Coppola, STMicroelectronics, France
Market, application and technology trends have always led to new challenges for the on-chip interconnections. These challenges have been the main driving factor of the evolutions for on-chip interconnections. This talk will describe the history of these evolutions, pointing out how a packet-switched on-chip micro-network (called in literature Network on Chip) is foreseen to be the next one of the current bus-based solution. Some well-known on-chip interconnection solutions are also classified in a specific time frame.

NoC the Arch key of IP integration methodology
Alain Fanet, Arteris, France
ARTERIS¹ Network on Chip (NoC) has been designed to enable the next generation of SoCs while taking advantage of existing IP, socket interfaces and design methods. SoC performance and complexity are enabled by advances in process technology, but those advances complicate the design of the communications between individual IP blocks or subsystems. Both IP designers and SoC integration teams are facing challenges in key areas including; How can we use current IP design techniques and advance to the next generation of SoC?; How can we take advantage of new process technologies and achieve both IP and SoC performance advances?; How can we guarantee interoperability of IP, regardless of the source?; How do we achieve the greatest ROI for both IP and SoC designs?; How do we address the rapidly escalating test and verification challenges? Arteris¹ NoC utilizes an innovative method of structuring the on-chip communications around well proven network techniques to deliver a cost effective solution to rapid SoC development. Not only does it utilize existing IP functions and subsystems, but provides a means of rapidly migrating to new process technologies. Products from Arteris are available today.

Networks on Chips: easing or complicating system architecture?
Kees Goossens, Embedded Systems Architectures on Silicon (ESAS) group, IC Design sector, Natuurkundig Laboratorium (NatLab), Philips Research , The Netherlands
The characteristics of on-chip communication are changing: wires are no longer pervasive, free, and infinitely fast, but their length, number, and performance have to be explicitly managed.  Networks on Chips (NOCs) promise to do this at the deep-submicron (back-end) level.  However, the change in characteristics also impacts the SOC/system architectures.  In this talk, we highlight some of the issues that must be addressed.  While NOCs are a central piece in a system architecture, they cannot solve all problems, and we discuss how other architecture components are affected too.  Examples are software abstractions, processing (processors, DMA, subsystems), and storage (scratch pads, caches, external memories).

Design for Yield
Yervant Zorian, Virage Logic, USA

The Design and Implementation of a First-Generation CELL Processor – A Multi-Core SuperComputer SoC
Dac C. Pham, STI-DC Chief Engineer and Global Convergence Manager, IBM Systems and Technology Group, Austin, USA
This talk describes the design and implementation of a first generation CELL Processor. The processor is a multi core SoC consisting of a 64 bit Power Architecture Processor Element (PPE) with an associated L2 memory subsystem, multiple Synergistic Processor Elements (SPE) each with its own local memory (LS), a high bandwidth internal Element Interconnect Bus (EIB), two configurable non-coherent I/O interfaces, a Memory Interface Controller (MIC), and a Pervasive unit that supports extensive test, monitoring, and debug functions. The design has roughly 234 million transistors implemented in 90nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high frequency clock rate. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

Formal methods in MpSoC architecture optimization
Rolf Ernst, TU Braunschweig, Germany
MpSoC architectures exhibit complex communication behavior that leads to sophisticated non-functional dependencies. Applications are increasingly dynamic and many system variants or application scenarios must be considered. In recent years, formal methods have been developed that support rapid design space exploration even for incomplete, non executable systems. New powerful features, such as sensitivity analysis, automated design parameter optimization, and worst case scenario generation, reach far beyond simulation approaches. Yet, lack of early design data in current design processes and remaining analysis limitations require an appropriate approach to embed such formal methods in the overall design process. The talk summarizes first experience mainly in automotive applications.

Multiprocessor architecture for consumer electronics SOC
Takao Nishitani, Kochi University of Technology, Japan

SoC Platforms of the Future: Challenges and Solutions
Pierre G. Paulin, Director, SoC Platform Automation, Advanced System Technology, STMicroelectronics Ottawa, Canada
This presentation will address the key challenges for the SoC platforms of the future, based on trends in STMicroelectronics' platforms in consumer video, imaging and audio applications.
We will also introduce some first elements of solutions to address these, with focus on the exploitation of small- to medium-grain parallelism, expressed in high-level platform programming models and mapped onto heterogeneous parallel H/W and S/W resources.

Optimization of Reliability and Power Consumption in MPSoCs
Tajana Simunic Rosing, CSE Department, UC San Diego, USA
Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature have made reliability assessment a much more significant issue in design. This talk focuses on the characterization of reliability at the system level for component-based Multi-Processor System on Chip designs. Reliability is strongly affected by system temperature, which is in turn driven by power consumption. Thus, component reliability and their power management should be addressed in tandem. A joint reliability and power management optimization problem is formulated whose solution is an optimal management policy. When careful joint policy optimization is performed, a significant improvement in energy consumption (40%) can be obtained in tandem with meeting reliability constraint for all operating temperatures.

Breaking the Interleaving Bottleneck in Communication Applications for Efficient SoC-Implementations
Norbert Wehn, University of Kaiserslautern, Germany
Interleaving is an important step on the physical layer in communication systems. It is used to minimize burst errors. Interleaving scrambles the data processing order to yield timing diversity. Sophisticated channel coding schemes like Turbo- or LDPC Codes heavily rely on it. However the interleaving process represents the bottleneck in high throughput architectures. In this talk we will discuss how to break this bottleneck to yield efficient SoC implementations.

Real Time Ray Tracing Algorithms for Next Generation CMP GPUs
Donald S. Fussell, Department of Computer Sciences, The University of Texas at Austin, USA
With the decline in ratio of computation cost to memory access cost and the availability of chip multiprocessors with reasonable amounts of on-chip memory, we have an opportunity for significant improvements in Graphics Processors (GPUs).  In particular, we now have enough computation available to render dynamic scenes with ray-traced global illumination effects at real-time rates.  GPUs optimized for such computations could produce much higher quality imagery than is possible using the constrained illuminatin model of today's z-buffer based GPUs.  A key challenge in realizing such systems is to perform ray tracing computations at memory efficiencies approaching those of z-buffer pipelines.  The latter need to retrieve the description of each object in the scene at most once, thus minimizing costly memory accesses. Ray tracers have traditionally not been able to approach this level of efficiency due to the fact that their evaluation of global illumination effects induces much less regular references to objects.
In this talk, we will describe our recent work on memory efficient ray tracing algorithms.  By changing the order in which rays and objects are processed, we can significantly improve on the memory efficiency of existing ray tracing algorithms.  We will also discuss how our new algorithmic approaches will map onto future GPUs, how well other global illumination effects map onto such machines, and what major challenges remain for achieving a new level of realistic realtime renderers.

New challenges in Smart Card design
Jean-Pierre Tual, Axalto, France
Hardware and Software concepts for smart cards have changed radically over the last 20 years. Initially conceived as rigid and monolithic devices constrained by « Security through obscurity » concerns, they are now more and relevant from up-to-date design paradigms in-spite of the (still) very limited resources and sharp environmental constraints they have to work with. Smart-Card design is in fact embarking a « HW-SW-Security » co-design approach, where multiple trade-offs have to be considered during the design steps. This paper will emphasize some major trends and challenges in modern smart-card design, focusing on crucial aspects linked to security management, including HW security and complex embedded (co)-processors, modern SW architecture, high-level proof of correctness, on-card telecommunication stacks, Web-service approach for network-centric cards, mobility and remote control protocols.

Power and Security Management in an NoC for Next Generation Mobile MPSoC's
Drew Wingard, CTO, Sonics Inc. USA
As the convergence of multimedia and data communications accelerates, handheld device SoC developers face increasingly modal designs. Power constraints demand that only the required processing units may be active in each mode, and at only the minimum required supply voltages to manage leakage current. Additionally, advanced handset designs must be able to deliver a flexible security environment where protected multimedia content and communications channels are protected from insecure code. This presentation focuses on several key features of the SonicsMX SMART Interconnect that enables SoC architects to manage balancing power and performance challenges. It will describe the topology options, power management architecture, security architecture, and the suggested design approach for using SonicsMX.

Surfing the wave of  Moore's law?
Rafael Peset Llopis, Philips IC Laboratory, Consumer Electronics, The Netherlands
The semiconductor industry has reached a critical point. In the past, manufacturers of (consumer) electronic products were financially able to develop their own ICs to do product innovation. Today's exploding engineering and mask costs have made the development of ICs only economically feasible for ICs with large volumes. In other words, only the semiconductor companies are able to develop today's SoC ICs for groups of customers. Hence, innovation can only be achieved by doing huge investments, while hoping to be able to sell in the future sufficient quantities to obtain benefit. Moving towards smaller technology nodes will result in even larger volume requirements for financial feasibility.
In this presentation we will give an overview of several technical possibilities to break with this trend.

Bridging the gap between semiconductor technology and design: a memory case study
Rudy Lauwereins, IMEC, Belgium
As semiconductor technologies continue to scale to sub 90 nm nodes, an increasing amount of technological barriers arise, such as increasing delays and static and dynamic energy consumption in both transistors and interconnect, thermal effects and impact of variability in yield, energy and delay. For most of these deep submicron (DSM) effects only point solutions leading to marginal improvements are in sight, when tackled from either a process technology, circuit or system design view point only. This presentation presents the results so far obtained for the Technology Aware Design program of IMEC which aims at establishing a methodology and supporting techniques and tools, to integrate and evaluate the possible solutions at these different abstraction levels into a global approach. It targets the design of better performing and robust applications and systems in spite of future DSM process technology limitations.
A cross-disciplinary team consisting of IMEC and K.U.Leuven researchers is following a novel approach to tackle these problems in a global way. The program is mainly targeting system-on-chip (SoC) designs for low-power wireless & multimedia applications, which are mainly data dominated. The program focuses on on-chip memory modules and their system organization. This presentation will highlight the program vision, challenges, objectives and results.

Multi-level Co-Simulation of Mixed Technology Microsystems
Steven P. Levitan, University of Pittsburgh, Department of Electrical and Computer Engineering, USA
The advent of highly integrated technologies such as MEMS, MOEMS, nanometer scale integrated circuits, mixed signal systems on a chip (SoC), and opto-electronic communication networks, requires flexible, sophisticated and efficient simulation tools. It is only through system level simulation based on behavioral models that efficient design space exploration can be performed across both architectural and implementation choices. In this talk, we present our solution based on a multi-level co-simulation environment for mixed domain micro and nano systems.

System level stimuli generation for the Cell processor
Roy Emek, IBM Research Laboratory in Haifa, Israel
In this talk, I will describe the architecture of the Cell processor, jointly developed by IBM, Sony and Toshiba. I will then discuss some of the system-level verification challenges encountered during the development of the Cell, and focus on various issues related to system-level stimuli generation.

Configurable Processor - the new NAND gate for MPSOC
Beatrice Fu, Senior Vice President, Engineering, Tensilica Inc., USA
This talk will describe the methodology of using configurable processors as building blocks for the increasingly complex SOC designs.  Like the conventional processors, configurable processors retain the advantage of full chip programmability.  But in contrast to the conventional processors, by rethinking the architecture and interfaces, configurable processors can deliver domain specific efficiency: high throughput, low cost and low power dissipation. Automation makes easy the creation and adoption of these tuned processors.  The underlying configurable processor architecture will be discussed and the automation tools that enables the emergence of this new methodology will be described.  A system design flow using multiple configurable processors and leveraging the automation tools will be included and illustrated with product examples.

The Sandbridge Sandblaster SB3000 Multithreaded CMP Platform
John Glossner, CTO & EVP, Sandbridge Technologies Inc., USA
From the end-user point of view, a modern communications device has a color screen, a keyboard, an antenna, audio, and video. All these features require high computing capability at low power consumption. Adding new features requires adding computing capability. The performance requirements for mobile wireless communication devices have expanded dramatically from their inception as mobile telephones. Consumers are demanding convergence devices with full data and voice integration as well as a variety of computationally intense features and applications such as web browsing, MP3 audio, and MPEG4 video. Moreover, consumers want these wireless subscriber services to be accessible at all times anywhere in the world.
Tremendous hardware and software challenges exist to realize convergence devices. Traditional communications systems have typically been implemented using custom hardware solutions. Chip rate, symbol rate, and bit rate co-processors are often coordinated by programmable DSPs but the DSP processor does not typically participate in computationally intensive tasks. When multiple communications systems requirements are considered, both silicon area and design validation are major inhibitors to commercial success. A software-based platform capable of dynamically reconfiguring and directly executing communications systems enables elegant reuse of silicon area and dramatically reduces time to market through software modifications instead of time consuming hardware redesigns.
Sandbridge Technologies has developed a scalable on-chip multiprocessor (CMP) for convergence markets. The processor is completely programmed in a high-level language (C or Java). Technical details will be disclosed of the multiprocessor, multithreaded (chip-level multithreading) vector DSP system including how the compiler automatically multithreads and vectorizes parallel applications and how the operating system kernel automatically maps software threads to hardware thread units. We will also describe results from the SB3010 4-core 32-thread chip now sampling and providing 10 billion multiply accumulates per second.

Measuring SMP
John Goodacre, ARM, UK
With symmetric multiprocessing (SMP) being asked to answer the hardware's challenge of power consumption and design cost, directly comes the question of logical vs. physical performance from the software designer. This talk takes a peak into the ongoing work inside www.eembc.org to bring a cross-platform industry standard benchmark suite for SMP devices. The comparison with uniprocessors, the challenge of portability and the layers of abstraction needed to show that your SMP device is the best!

A class-based programming model for heterogeneous MPSoC
Mark Lippett, Ignios Ltd., UK
The prerequisites for an efficient class-based abstraction for heterogeneous SoC will be discussed. The speaker will demonstrate software written using one such class-based abstraction running on various configurations of SoC and will explore the flexibility and efficiency that can be offered to the embedded software developer using such an approach.

Linux real-time capabilities for SMP SoC platforms
Philippe Kajfasz, Thales, Land and Joint Systems, France
Operating systems supporting SMP architectures provide to application designers simple and flexible services for exploiting execution parallelism. We present some real-time capabilities that have been added to Linux for SMP machines and how this can be applied to MPSoC with additional embeddability constraints. Finally, we present future trends for operating systems in SoC-based real-time embedded systems.

Redefis:  An SoC Platform for Implementing Application-Specific or User-Custom Logic
Kazuaki Murakami, Kyushu University, Computing and Communications Center, Department of Informatics, Japan
Redefis is an SoC platform which aims at implementing application-specific or user-custom logic on SoC's by means of providing instruction-set reconfigurable processors and corresponding design tools to be used in SoC designs.  One important design tool is the instruction generator whose goal is to generated an optimized and specific instruction set for a given program (C).  The tool combines library-based C-level model recognition and replacing with synthesis for generating the instructions sets.  Another important vehicle for Redefis is the dynamically reconfigurable processor which can reconfigure the datapath at the instruction-set by instruction-set basis (coarse grain) or instruction-by-instruction basis (fine grain).

SOC: Security-on-chip!
Srivaths Ravi, NEC Laboratories America, USA
Embedded electronic systems such as cellphones, PDAs, sensors, etc., which are increasingly becoming a ubiquitous component of our everyday lives, are routinely used to capture, store, manipulate, and access sensitive data. However, as these systems become more extensible and more networked, we find that they have progressively become very complex. As a consequence, attacks on information security, which have hitherto been the bane of general-purpose computing systems, are alarmingly a concern for embedded systems. Conventionally, designers of SOCs for these devices have had to focus on elements such as cost, performance, power, or testability. But, it is increasingly apparent that unless security is factored in throughout the design process, it would be too late or too expensive to do anything in the postmortem of an attack.
In this talk, I will first highlight the challenges encountered in the design of security-aware SOCs for embedded systems. Using real-world examples, we will identify the security concerns of various parties involved in an embedded system value chain: secure communications, secure storage, trusted authentication, digital rights management, etc. We will then discuss how these translate into design challenges that must be addressed --- security processing gap, battery gap, flexibility, assurance gap (given the multitude of physical, side-channel, and software attacks), etc. - and are ushering in a need for security-aware design. I will then outline the design tradeoffs involved as well as the solutions adopted in practice. Finally, I will present MOSES - a security architecture developed by us for an application SOC used in NEC's 3G cell phones.

Sub-Lithographic Semiconductor Computing Systems
André DeHon, California Institute of Technology, USA
We can now engineer designed nanostructures without using lithography.  Design at this scale, however, will not simply be an extension of our familiar VLSI design.  We may not be able to directly pattern complex features, but rather must exploit basic physical properties to define feature sizes, self-assembly to create ordered devices, and post-fabrication reconfigurability to define functionality and mask defects. I will review the emerging nanoscale fabrication building blocks, sketch a hybrid fabrication scheme which uses these building blocks along with lithography, and present a plausible architecture for nanoscale electronics based on silicon nanowires.  I demonstrate that these nanoscale constructs are sufficient to provide universal logic functionality with all logic and signal restoration operating at the nanoscale.

Self-Calibrating Interconnects: Breaking the Worst-Case Design Paradigm
Paolo Ienne, EPFL, Switzerland
As semiconductor technologies scale down, it is harder to control critical electrical parameters both at manufacturing time and during operation. In other words, design parameters have a wider statistical spread around their nominal values than they had in the past. Typical VLSI design methodologies assume operation in worst-case conditions--that is, in conditions whose probability is inconsequentially small. In the future, due to the large spread, this approach may fail to leverage the improvements of new technologies. The design of digital self-calibrating circuits can be an effective answer to the problem. The talk illustrates the potentials of this technique by applying it to long interconnection busses, where the operating parameters (in this case swing voltage and data rate) are determined on-line, based on the actual operating conditions of the circuit. The various key challenges involved in implementing self-calibrating circuits in practice will be discussed.

MPSoC clock and power challenges
Olivier Franza, Digital Clock Generation, Distribution, & Power Group, Intel Massachusetts, Inc., USA
Microprocessor performance and power efficiency are rapidly leading the industry away from a frequency-centric single-core paradigm towards MPSoC models long used in wireless and embedded systems. Time to market pressure to leverage the compressed technology window and more parallelism-friendly software applications (allowing for distinct software threads) thrust multiple core proliferation on die rather than single complex cores.
The on-die coexistence of multiple, possibly heterogeneous, functional blocks under stringent thermal limits leads to new challenges for both clock and power infrastructure design, advocating for smarter power management schemes to optimize performance —like self optimization or frequency adaptability— and introducing clock domain data transfers to latency and determinism (repeatability and predictability) requirement issues.
This presentation will assess the current state of the art of clock and power methodologies and techniques developed for MPSoC microprocessor design and give some direction leads for the future.

MeP (Media Embedded Processor), a configurable and extensible microprocessor designed for heterogeneous multi-processor SoC
Masataka Matsui, Senior Manager, Digital Media SoC (System-on-a-Chip) Dept., SoC Research & Development Center, Toshiba Corp., Japan
MeP, a 32-bit configurable embedded microprocessor, is integrated on a various MPSoC's such as a single-chip HD DTV decoder, an automotive image recognition LSI and a mobile video-application processor. In these SoC's MeP is used with various extensions such as a VLIW audio DSP coprocessor and an MPEG4 video codec hardware engine.
This talk presents a review of the architecture, tools and co-design flow of MeP with some MPSoC applications, which would show that MeP is by nature developed for heterogeneous MPSoC.

Industrial usage of C-based synthesis and verification
Kazutoshi Wakabayashi, System CAD, System Devices Res. Labs. NEC Corp., Japan
We present how C-based behavioral synthesis is practically used for various chips. Though C-based behavioral syntheis has been thought as a toy tool, but, several million dollar chip are designed by C-based synthesis in NEC last year. The chips are not only for Data flow type application such as DCT, FEC, encription, but also controll dominated circuits such as DMA controller, bus bridge, timer, seqecenser, CPU. We will introduce our design environment and show some stastical data on design efficiency and simulation efficiency.

Synchronous Debugging of Multicore Systems
Vojin Zivojnovic, VP ESL Tools, Development Systems group, ARM Inc., Irvine CA, USA

Multithreaded processors in embedded applications
Steffen Buch, Infineon Technologies AG, Germany
Memory access becomes more and more the bottleneck in embedded processor applications. Often deep memory hierachies up to three levels (L1-, L2-cache and main memory) are used to alleviate this effect. Especially large on-chip L2 caches are very expensive and power hungry. Furthermore applications demand higher performance but clock speeds of embedded processors do not increase very quickly beacause of memory access and power issues. One solution, with a big impact on area however, are multi-processor systems. Another way of increasing the effective processor performance with only a modest overhead in terms of area is multi-threading.
In this talk scenarios for the application of multi-threaded processors in SoC designs are presented and different aspects such as balanced system design and programming models. With an analogy to modern communication systems an idea how to apply multithreading to increase performance of MPSoCs is given. Finally, two examples for multi-threaded processor designs at Infineon are presented.

Flexible CPUs for SoC Design
Trevor Mudge, University of Michigan, USA
This talk will overview flexible CPUs and their use in SOCs. We will examine CPUs that are morphable at run-time, such as those offered by FPGA vendors Xilinx and Altera. We will also examine those that are morphable at design time such as the solutions offered by Tensilica and ARC. We will discuss the cost of flexibility by comparing and contrasting implementations as ASICs, structured ASIC, or an FPGAs. The impact on SOC power will also be discussed.

Multiprocessor SoCs: why is it so hard to define and program these architectures ?
Frédéric Pétrot, TIMA Laboratory, France
People of the high performance computing field have struggled for years trying to program their highly regular parallel machines in an efficient way to solve numerical problems. The emergence of heterogeneous and ad-hoc MPSoC platforms for consumer applications makes it even worse to define architectures and programming models that exploits at best the hardware and software processing power provided by these platforms.
The talk reviews hardware level program execution on an MPSoC architecture and pinpoints implementation aspects that are worth considering to meet applications constraints. It also gives a few hints on actual solutions.

Communication Platforms for Network-on-Chip
Hannu Tenhunen, School of Information Technology, Royal Institute of Technology (KTH), Sweden

Everything I know about software radio in 10 minutes or less
Wayne Wolf, Princeton University, USA
Software defined radios and cognitive radios promise more powerful and secure communications by taking advantage of programmable digital systems. However, both the hardware and software for a software-defined radio must be carefully architected, particularly if they are to operate from batteries.  This talk will introduce some basic concepts in software-defined radio and identify some design challenges.