Opening Session: Keynotes
  • Opening Keynote: Digital Media – The New Frontier for Supercomputing
    Lisa Su, VP, Technology Development and Alliances, IBM Systems and Technology Group, Hopewell Junction NY, USA
    Mention a supercomputer and most people would visualize a room full of specialized computer equipment. The insatiable appetite of the video game developer community for photo realistic graphics and real time network interaction requires tremendous computing power and is driving the effort to develop a supercomputer on a chip. Advancements in semiconductor process technology such as silicon-on-insulator (SOI) technology, strained silicon techniques and low dielectric constant materials coupled with architectural enhancements such as multi-core microprocessors, high speed broadband I/O and memory, and floating point processing power bring supercomputer performance to consumer applications. These advances will change the look and feel of digital media applications in the future and will enable a platform for continued innovation.
  • Nomadik: an MPSoC solution for advanced Multimedia
    Alain Artieri, Director of Engineering, Application Processor and Portable Platforms Division, STMicroelectronics, Grenoble France
Tutorial Session T1: MPSoC: HW Challenges
  • Reliability and design of SoCs for reliability
    Giovanni De Micheli, EPFL, Switzerland
    Whereas research and development on reliable systems has permeated the last three decades, a renewed interest on single-chip reliability has been fueled by the technological progress, namely by the extremely small nature of electronic devices, the extremely large complexity of systems, and the new, uncharted territory set by nanotechnologies. This tutorial will review the basic models of semiconductor failures as well as the theory an practice of reliable system design. We will focus on physical and mathematical modeling, as well as on computational methods to asses reliability.
  • Configurable Core Generation for Multi-Processor SoC
    Masaharu Imai, Graduate School of Information Science and Technology, Osaka University, Suita, Japan
    This talk describes the state-of-the-art technology of the configurable processor core generation. First, the role of configurable processor core in the future MPSoC is described. Then the requirements to these processor cores are analyzed. Next, the generation technologies of configurable processor core and of application software development tools, including compiler, assembler, and ISS, are introduced. Finally, case studies of application domain specific processors based on configurable processor cores are shown.
Tutorial Session T2: MPSoC: SW Challenges
  • Foundations for Model-Based Design
    Janos Sztipanovits, ISIS-Vanderbilt University, USA
    Modeling, model analysis, model transformation and model-based code generation play fundamental role in integrated systems/software design. These steps use models, which are formal, composable and manipulable during the design process. The modeling languages, in which models are expressed, are domain-specific, offering system designers modeling constructs and syntax that are close to their application domain. In model-based design, domain-specific modeling languages (DSMLs) are used to capture the structural and behavioral aspects of embedded software and systems. Their semantics emphasize concurrency, communication abstractions, temporal and other physical properties. The goal of this tutorial is to review the state-of-the-art in the precise syntactic and semantic specification of DSMLs and to show their practical use in building integrated tool chains.
  • Software-Centric System-Level Design
    Hiroaki Takada
    , Nagoya University, Graduate School of Information Science, Japan
Session 1: From Networking to Network-on-Chip
  • On-Chip Interconnects: Circuits and Signaling from an MPSOC Perspective
    Wayne Burleson, ECE Dept., University of Massachusetts Amherst, USA
    This talk presents recent work in interconnect circuit modeling below 90nm CMOS emphasizing estimators for delay and power while accounting for noise and variations. Several new circuit and signaling techniques are presented which show improved speed and both dynamic and static power consumption while retaining robust behavior even in the presence of deep sub-micron effects. This talk has been groomed for the MPSOC audience to allow careful abstraction of interconnect issues thus allowing system-level design of global interconnects, buses and networks on chip, while also exposing several promising future directions.
  • Global Networking versus Networking-on-Chip
    Martina Zitterbart, Institute of Telematics, University of Karlsruhe (TH) Germany
Session 2: Network-on-Chip
  • NoCs: pushing toward the back-end
    Luca Benini
    , DEIS, University of Bologna, Italy 
    Network-on-chips are gaining momentum as the interonnection fabric for fabric of choice for future MPSoCs. Architectural scalability trends and  design technology arguments are favorable to the NoC approach, but designers want hard facts and they need solutions that do not require disruptive changes in design technology.  In this talk we will look into the experience and lessons learned in developing a complete back-end flow for NoC deployment in current real-life silicon technology.
  • From spaghetti wires to NoC
    Marcello Coppola, STMicroelectronics, France
    Market, application and technology trends have always led to new challenges for the on-chip interconnections. These challenges have been the main driving factor of the evolutions for on-chip interconnections. This talk will describe the history of these evolutions, pointing out how a packet-switched on-chip micro-network (called in literature Network on Chip) is foreseen to be the next one of the current bus-based solution. Some well-known on-chip interconnection solutions are also classified in a specific time frame.
  • NoC the Arch key of IP integration methodology
    Alain Fanet
    , Arteris, France
    ARTERIS¹ Network on Chip (NoC) has been designed to enable the next generation of SoCs while taking advantage of existing IP, socket interfaces and design methods. SoC performance and complexity are enabled by advances in process technology, but those advances complicate the design of the communications between individual IP blocks or subsystems. Both IP designers and SoC integration teams are facing challenges in key areas including; How can we use current IP design techniques and advance to the next generation of SoC?; How can we take advantage of new process technologies and achieve both IP and SoC performance advances?; How can we guarantee interoperability of IP, regardless of the source?; How do we achieve the greatest ROI for both IP and SoC designs?; How do we address the rapidly escalating test and verification challenges? Arteris¹ NoC utilizes an innovative method of structuring the on-chip communications around well proven network techniques to deliver a cost effective solution to rapid SoC development. Not only does it utilize existing IP functions and subsystems, but provides a means of rapidly migrating to new process technologies. Products from Arteris are available today.
  • Networks on Chips: easing or complicating system architecture?
    Kees Goossens, Embedded Systems Architectures on Silicon (ESAS) group, IC Design sector, Natuurkundig Laboratorium (NatLab), Philips Research , The Netherlands
    The characteristics of on-chip communication are changing: wires are no longer pervasive, free, and infinitely fast, but their length, number, and performance have to be explicitly managed.  Networks on Chips (NOCs) promise to do this at the deep-submicron (back-end) level.  However, the change in characteristics also impacts the SOC/system architectures.  In this talk, we highlight some of the issues that must be addressed.  While NOCs are a central piece in a system architecture, they cannot solve all problems, and we discuss how other architecture components are affected too.  Examples are software abstractions, processing (processors, DMA, subsystems), and storage (scratch pads, caches, external memories).
  • Design for Yield
    Yervant Zorian, Virage Logic, USA
Session 3: The CELL Architecture
  • Cell Architecture and Broadband Engine Processor
    Ted Maeurer, Cell Software Center Manager, Sony - Toshiba - IBM Design Center, IBM Systems & Technology Group, Austin, USA
  • The Design and Implementation of a First-Generation CELL Processor – A Multi-Core SuperComputer SoC
    Dac C. Pham, STI-DC Chief Engineer and Global Convergence Manager, IBM Systems and Technology Group, Austin, USA
    This talk describes the design and implementation of a first generation CELL Processor. The processor is a multi core SoC consisting of a 64 bit Power Architecture Processor Element (PPE) with an associated L2 memory subsystem, multiple Synergistic Processor Elements (SPE) each with its own local memory (LS), a high bandwidth internal Element Interconnect Bus (EIB), two configurable non-coherent I/O interfaces, a Memory Interface Controller (MIC), and a Pervasive unit that supports extensive test, monitoring, and debug functions. The design has roughly 234 million transistors implemented in 90nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high frequency clock rate. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.
Session 4: MPSoC Platforms
  • Formal methods in MpSoC architecture optimization
    Rolf Ernst, TU Braunschweig, Germany
    MpSoC architectures exhibit complex communication behavior that leads to sophisticated non-functional dependencies. Applications are increasingly dynamic and many system variants or application scenarios must be considered. In recent years, formal methods have been developed that support rapid design space exploration even for incomplete, non executable systems. New powerful features, such as sensitivity analysis, automated design parameter optimization, and worst case scenario generation, reach far beyond simulation approaches. Yet, lack of early design data in current design processes and remaining analysis limitations require an appropriate approach to embed such formal methods in the overall design process. The talk summarizes first experience mainly in automotive applications.
  • Multiprocessor architecture for consumer electronics SOC
    Takao Nishitani, Kochi University of Technology, Japan
  • SoC Platforms of the Future: Challenges and Solutions
    Pierre G. Paulin, Director, SoC Platform Automation, Advanced System Technology, STMicroelectronics Ottawa, Canada
    This presentation will address the key challenges for the SoC platforms of the future, based on trends in STMicroelectronics' platforms in consumer video, imaging and audio applications.
    We will also introduce some first elements of solutions to address these, with focus on the exploitation of small- to medium-grain parallelism, expressed in high-level platform programming models and mapped onto heterogeneous parallel H/W and S/W resources.
  • Optimization of Reliability and Power Consumption in MPSoCs
    Tajana Simunic Rosing, CSE Department, UC San Diego, USA
    Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature have made reliability assessment a much more significant issue in design. This talk focuses on the characterization of reliability at the system level for component-based Multi-Processor System on Chip designs. Reliability is strongly affected by system temperature, which is in turn driven by power consumption. Thus, component reliability and their power management should be addressed in tandem. A joint reliability and power management optimization problem is formulated whose solution is an optimal management policy. When careful joint policy optimization is performed, a significant improvement in energy consumption (40%) can be obtained in tandem with meeting reliability constraint for all operating temperatures.
  • Breaking the Interleaving Bottleneck in Communication Applications for Efficient SoC-Implementations
    Norbert Wehn, University of Kaiserslautern, Germany
    Interleaving is an important step on the physical layer in communication systems. It is used to minimize burst errors. Interleaving scrambles the data processing order to yield timing diversity. Sophisticated channel coding schemes like Turbo- or LDPC Codes heavily rely on it. However the interleaving process represents the bottleneck in high throughput architectures. In this talk we will discuss how to break this bottleneck to yield efficient SoC implementations.
Session 5: MPSoC: Theory & Practices
  • Real Time Ray Tracing Algorithms for Next Generation CMP GPUs
    Donald S. Fussell
    , Department of Computer Sciences, The University of Texas at Austin, USA
    With the decline in ratio of computation cost to memory access cost and the availability of chip multiprocessors with reasonable amounts of on-chip memory, we have an opportunity for significant improvements in Graphics Processors (GPUs).  In particular, we now have enough computation available to render dynamic scenes with ray-traced global illumination effects at real-time rates.  GPUs optimized for such computations could produce much higher quality imagery than is possible using the constrained illuminatin model of today's z-buffer based GPUs.  A key challenge in realizing such systems is to perform ray tracing computations at memory efficiencies approaching those of z-buffer pipelines.  The latter need to retrieve the description of each object in the scene at most once, thus minimizing costly memory accesses. Ray tracers have traditionally not been able to approach this level of efficiency due to the fact that their evaluation of global illumination effects induces much less regular references to objects.
    In this talk, we will describe our recent work on memory efficient ray tracing algorithms.  By changing the order in which rays and objects are processed, we can significantly improve on the memory efficiency of existing ray tracing algorithms.  We will also discuss how our new algorithmic approaches will map onto future GPUs, how well other global illumination effects map onto such machines, and what major challenges remain for achieving a new level of realistic realtime renderers.
  • New challenges in Smart Card design
    Jean-Pierre Tual, Axalto, France
    Hardware and Software concepts for smart cards have changed radically over the last 20 years. Initially conceived as rigid and monolithic devices constrained by « Security through obscurity » concerns, they are now more and relevant from up-to-date design paradigms in-spite of the (still) very limited resources and sharp environmental constraints they have to work with. Smart-Card design is in fact embarking a « HW-SW-Security » co-design approach, where multiple trade-offs have to be considered during the design steps. This paper will emphasize some major trends and challenges in modern smart-card design, focusing on crucial aspects linked to security management, including HW security and complex embedded (co)-processors, modern SW architecture, high-level proof of correctness, on-card telecommunication stacks, Web-service approach for network-centric cards, mobility and remote control protocols.
  • Power and Security Management in an NoC for Next Generation Mobile MPSoC's
    Drew Wingard, CTO, Sonics Inc. USA
    As the convergence of multimedia and data communications accelerates, handheld device SoC developers face increasingly modal designs. Power constraints demand that only the required processing units may be active in each mode, and at only the minimum required supply voltages to manage leakage current. Additionally, advanced handset designs must be able to deliver a flexible security environment where protected multimedia content and communications channels are protected from insecure code. This presentation focuses on several key features of the SonicsMX SMART Interconnect that enables SoC architects to manage balancing power and performance challenges. It will describe the topology options, power management architecture, security architecture, and the suggested design approach for using SonicsMX.
Session 6: Technologies for MPSoC
  • Surfing the wave of  Moore's law?
    Rafael Peset Llopis, Philips IC Laboratory, Consumer Electronics, The Netherlands
    The semiconductor industry has reached a critical point. In the past, manufacturers of (consumer) electronic products were financially able to develop their own ICs to do product innovation. Today's exploding engineering and mask costs have made the development of ICs only economically feasible for ICs with large volumes. In other words, only the semiconductor companies are able to develop today's SoC ICs for groups of customers. Hence, innovation can only be achieved by doing huge investments, while hoping to be able to sell in the future sufficient quantities to obtain benefit. Moving towards smaller technology nodes will result in even larger volume requirements for financial feasibility.
    In this presentation we will give an overview of several technical possibilities to break with this trend.
  • Bridging the gap between semiconductor technology and design: a memory case study
    Rudy Lauwereins, IMEC, Belgium
    As semiconductor technologies continue to scale to sub 90 nm nodes, an increasing amount of technological barriers arise, such as increasing delays and static and dynamic energy consumption in both transistors and interconnect, thermal effects and impact of variability in yield, energy and delay. For most of these deep submicron (DSM) effects only point solutions leading to marginal improvements are in sight, when tackled from either a process technology, circuit or system design view point only. This presentation presents the results so far obtained for the Technology Aware Design program of IMEC which aims at establishing a methodology and supporting techniques and tools, to integrate and evaluate the possible solutions at these different abstraction levels into a global approach. It targets the design of better performing and robust applications and systems in spite of future DSM process technology limitations.
    A cross-disciplinary team consisting of IMEC and K.U.Leuven researchers is following a novel approach to tackle these problems in a global way. The program is mainly targeting system-on-chip (SoC) designs for low-power wireless & multimedia applications, which are mainly data dominated. The program focuses on on-chip memory modules and their system organization. This presentation will highlight the program vision, challenges, objectives and results.
  • Multi-level Co-Simulation of Mixed Technology Microsystems
    Steven P. Levitan, University of Pittsburgh, Department of Electrical and Computer Engineering, USA
    The advent of highly integrated technologies such as MEMS, MOEMS, nanometer scale integrated circuits, mixed signal systems on a chip (SoC), and opto-electronic communication networks, requires flexible, sophisticated and efficient simulation tools. It is only through system level simulation based on behavioral models that efficient design space exploration can be performed across both architectural and implementation choices. In this talk, we present our solution based on a multi-level co-simulation environment for mixed domain micro and nano systems.
  • Soft Errors: Interactions with Power Optimization
    Vijaykrishnan Narayanan
    , Computer Science and Engineering Department, Pennsylvania State U., USA
    Soft errors are radiation induced ionization events that cause errors in circuits. Reliability issues due to soft errors are gaining increased prominence in nanometer technologies as the reduced nodal capacitances and supply voltages coupled with integration of multiple cores on a single chip are increasing chip soft error rates (SER). A hierarchical soft error analysis toolset, SEAT, is being developed at Penn State to help combat the soft error problem and evaluate the influence of different system design decisions on reliability. After introducing this toolset, the talk will highlight the interactions between SER and power consumption. First, we will show how some commonly used power optimizations impact SER. Next, we will discuss the influence of additional power consumed by techniques designed to combat soft error problems and demonstrate the use of adaptive techniques to strike a balance between desired SER and power budget.
  • System level stimuli generation for the Cell processor
    Roy Emek, IBM Research Laboratory in Haifa, Israel
    In this talk, I will describe the architecture of the Cell processor, jointly developed by IBM, Sony and Toshiba. I will then discuss some of the system-level verification challenges encountered during the development of the Cell, and focus on various issues related to system-level stimuli generation.
Session 7: HW & SW Programming for MPSoC
  • Configurable Processor - the new NAND gate for MPSOC
    Beatrice Fu, Senior Vice President, Engineering, Tensilica Inc., USA
    This talk will describe the methodology of using configurable processors as building blocks for the increasingly complex SOC designs.  Like the conventional processors, configurable processors retain the advantage of full chip programmability.  But in contrast to the conventional processors, by rethinking the architecture and interfaces, configurable processors can deliver domain specific efficiency: high throughput, low cost and low power dissipation. Automation makes easy the creation and adoption of these tuned processors.  The underlying configurable processor architecture will be discussed and the automation tools that enables the emergence of this new methodology will be described.  A system design flow using multiple configurable processors and leveraging the automation tools will be included and illustrated with product examples.
  • The Sandbridge Sandblaster SB3000 Multithreaded CMP Platform
    John Glossner, CTO & EVP, Sandbridge Technologies Inc., USA
    From the end-user point of view, a modern communications device has a color screen, a keyboard, an antenna, audio, and video. All these features require high computing capability at low power consumption. Adding new features requires adding computing capability. The performance requirements for mobile wireless communication devices have expanded dramatically from their inception as mobile telephones. Consumers are demanding convergence devices with full data and voice integration as well as a variety of computationally intense features and applications such as web browsing, MP3 audio, and MPEG4 video. Moreover, consumers want these wireless subscriber services to be accessible at all times anywhere in the world.
    Tremendous hardware and software challenges exist to realize convergence devices. Traditional communications systems have typically been implemented using custom hardware solutions. Chip rate, symbol rate, and bit rate co-processors are often coordinated by programmable DSPs but the DSP processor does not typically participate in computationally intensive tasks. When multiple communications systems requirements are considered, both silicon area and design validation are major inhibitors to commercial success. A software-based platform capable of dynamically reconfiguring and directly executing communications systems enables elegant reuse of silicon area and dramatically reduces time to market through software modifications instead of time consuming hardware redesigns.
    Sandbridge Technologies has developed a scalable on-chip multiprocessor (CMP) for convergence markets. The processor is completely programmed in a high-level language (C or Java). Technical details will be disclosed of the multiprocessor, multithreaded (chip-level multithreading) vector DSP system including how the compiler automatically multithreads and vectorizes parallel applications and how the operating system kernel automatically maps software threads to hardware thread units. We will also describe results from the SB3010 4-core 32-thread chip now sampling and providing 10 billion multiply accumulates per second.
  • Flexible multiprocessing memory architectures
    Kees Vissers,  Principal engineer, Xilinx Research, USA
    When you take a good look at the silicon area of todays fixed MPSoCs you will see that the area is dominated by memory. This is true for high-end Intel processors, low-power and high-performance Sandbridge solutions, and for the novel ST multi-threaded multi-processor architectures.
    Part of the problem is that you try to fix the memory architecture before you know the problem. In this talk I will illustrate that a problem specific streaming memory architecture, connecting multiple processing elements, has many desirable characteristics. I will show that building these problem specific solutions out of a range of memory elements with programmable interconnect is a very powerful solution. This can avoid using slow buses, or high-latency on chip networks.
    This will be illustrated with actual implementations on existing FPGA platforms. The examples will include the high-level programming models, the mapping tools and the implementations. The examples will include cost effective HDTV resolution video codecs,multiple channel MPEG4 decoders, and a 16 channel, of 1Gbps each, router with low latency.
Session 8: Application of Programming Models
  • Measuring SMP
    John Goodacre, ARM, UK
    With symmetric multiprocessing (SMP) being asked to answer the hardware's challenge of power consumption and design cost, directly comes the question of logical vs. physical performance from the software designer. This talk takes a peak into the ongoing work inside to bring a cross-platform industry standard benchmark suite for SMP devices. The comparison with uniprocessors, the challenge of portability and the layers of abstraction needed to show that your SMP device is the best!
  • A class-based programming model for heterogeneous MPSoC
    Mark Lippett, Ignios Ltd., UK
    The prerequisites for an efficient class-based abstraction for heterogeneous SoC will be discussed. The speaker will demonstrate software written using one such class-based abstraction running on various configurations of SoC and will explore the flexibility and efficiency that can be offered to the embedded software developer using such an approach.
  • Linux real-time capabilities for SMP SoC platforms
    Philippe Kajfasz, Thales, Land and Joint Systems, France
    Operating systems supporting SMP architectures provide to application designers simple and flexible services for exploiting execution parallelism. We present some real-time capabilities that have been added to Linux for SMP machines and how this can be applied to MPSoC with additional embeddability constraints. Finally, we present future trends for operating systems in SoC-based real-time embedded systems.
  • Redefis:  An SoC Platform for Implementing Application-Specific or User-Custom Logic
    Kazuaki Murakami
    , Kyushu University, Computing and Communications Center, Department of Informatics, Japan
    Redefis is an SoC platform which aims at implementing application-specific or user-custom logic on SoC's by means of providing instruction-set reconfigurable processors and corresponding design tools to be used in SoC designs.  One important design tool is the instruction generator whose goal is to generated an optimized and specific instruction set for a given program (C).  The tool combines library-based C-level model recognition and replacing with synthesis for generating the instructions sets.  Another important vehicle for Redefis is the dynamically reconfigurable processor which can reconfigure the datapath at the instruction-set by instruction-set basis (coarse grain) or instruction-by-instruction basis (fine grain).
  • SOC: Security-on-chip!
    Srivaths Ravi, NEC Laboratories America, USA
    Embedded electronic systems such as cellphones, PDAs, sensors, etc., which are increasingly becoming a ubiquitous component of our everyday lives, are routinely used to capture, store, manipulate, and access sensitive data. However, as these systems become more extensible and more networked, we find that they have progressively become very complex. As a consequence, attacks on information security, which have hitherto been the bane of general-purpose computing systems, are alarmingly a concern for embedded systems. Conventionally, designers of SOCs for these devices have had to focus on elements such as cost, performance, power, or testability. But, it is increasingly apparent that unless security is factored in throughout the design process, it would be too late or too expensive to do anything in the postmortem of an attack.
    In this talk, I will first highlight the challenges encountered in the design of security-aware SOCs for embedded systems. Using real-world examples, we will identify the security concerns of various parties involved in an embedded system value chain: secure communications, secure storage, trusted authentication, digital rights management, etc. We will then discuss how these translate into design challenges that must be addressed --- security processing gap, battery gap, flexibility, assurance gap (given the multitude of physical, side-channel, and software attacks), etc. - and are ushering in a need for security-aware design. I will then outline the design tradeoffs involved as well as the solutions adopted in practice. Finally, I will present MOSES - a security architecture developed by us for an application SOC used in NEC's 3G cell phones.
Session 9: Beyond SoC Practices
  • Sub-Lithographic Semiconductor Computing Systems
    André DeHon
    , California Institute of Technology, USA
    We can now engineer designed nanostructures without using lithography.  Design at this scale, however, will not simply be an extension of our familiar VLSI design.  We may not be able to directly pattern complex features, but rather must exploit basic physical properties to define feature sizes, self-assembly to create ordered devices, and post-fabrication reconfigurability to define functionality and mask defects. I will review the emerging nanoscale fabrication building blocks, sketch a hybrid fabrication scheme which uses these building blocks along with lithography, and present a plausible architecture for nanoscale electronics based on silicon nanowires.  I demonstrate that these nanoscale constructs are sufficient to provide universal logic functionality with all logic and signal restoration operating at the nanoscale.
  • Self-Calibrating Interconnects: Breaking the Worst-Case Design Paradigm
    Paolo Ienne
    , EPFL, Switzerland
    As semiconductor technologies scale down, it is harder to control critical electrical parameters both at manufacturing time and during operation. In other words, design parameters have a wider statistical spread around their nominal values than they had in the past. Typical VLSI design methodologies assume operation in worst-case conditions--that is, in conditions whose probability is inconsequentially small. In the future, due to the large spread, this approach may fail to leverage the improvements of new technologies. The design of digital self-calibrating circuits can be an effective answer to the problem. The talk illustrates the potentials of this technique by applying it to long interconnection busses, where the operating parameters (in this case swing voltage and data rate) are determined on-line, based on the actual operating conditions of the circuit. The various key challenges involved in implementing self-calibrating circuits in practice will be discussed.
  • MPSoC clock and power challenges
    Olivier Franza, Digital Clock Generation, Distribution, & Power Group, Intel Massachusetts, Inc., USA
    Microprocessor performance and power efficiency are rapidly leading the industry away from a frequency-centric single-core paradigm towards MPSoC models long used in wireless and embedded systems. Time to market pressure to leverage the compressed technology window and more parallelism-friendly software applications (allowing for distinct software threads) thrust multiple core proliferation on die rather than single complex cores.
    The on-die coexistence of multiple, possibly heterogeneous, functional blocks under stringent thermal limits leads to new challenges for both clock and power infrastructure design, advocating for smarter power management schemes to optimize performance —like self optimization or frequency adaptability— and introducing clock domain data transfers to latency and determinism (repeatability and predictability) requirement issues.
    This presentation will assess the current state of the art of clock and power methodologies and techniques developed for MPSoC microprocessor design and give some direction leads for the future.
Session 10: Programming Models for MPSoC
  • Cross-layer Modelling for Heterogeneous MPSoCs
    Jan Madsen
    , Technical University of Denmark, Department of Informatics and Mathematical Modelling, Denmark
    One of the challenges of designing a heterogeneous multiprocessor SoC is to find the right partitioning of the application onto the platform architecture. The right partitioning is dependent on the characteristics of the processors and the network connecting them, as well as the application. We present a system-level modelling framework (ARTS) which allows for cross-layer modelling and analysis, covering application layer, middelware layer, and hardware layer. ARTS allow the designer to explore and analyse; the network performance under different traffic and load conditions, consequences of different mappings of tasks to processors (software or hardware) including memory usage, and effects of RTOS selection, including scheduling, synchronization and resource allocation policies. In this presentation we focus on the programmer's view illustrated through a design space exploration of a multi-mode multimedia application mapped onto an MPSoC platform.
  • Specification and Validation for Heterogeneous Systems
    Gabriela Nicolescu
    , Ecole Polytechnique de Montréal, Canada
    Systems on chip are presently drivers for convergence of multiple technologies, this new trend promising more efficient MPSoCs. The design of these systems will require new CAD tools able to accommodate various concepts specific to different application domains (e.g. optical, mechanical, electrical, etc.). This presentation will investigate the challenges for defining and implementing simulation-based validation tools. Some complex execution models implied by these tools are also presented.
  • Parallel Programming Model for Distributed Architecture MPSoC
    Yuriy Sheynin
    , St. Petersburg State University of Aerospace Instrumentation, Russia
    Heterogeneous distributed scalable architectures with coarse-grained cores are the trend in embedded MPSoC to provide high performance and ensure power efficiency. Programming of coarse-grained heterogeneous MPSoC remains a challenging task that requires new parallel programming paradigms and computational models for procedure-level and task-level parallelism.
    Features of static and dynamic parallel computations are discussed. The AGP-model (“Asynchronous Growing Processes”) of parallel computations is presented as a formal basis for Parallel programming model that covers dynamic and static parallel computations in MPSoC. The introduced Parallel programming model splits programming into programming of a parallel program scheme and programming of its nodes interpretation. A parallel program scheme is explicitly programmed in the parallel programming language Visa , which is based on the AGP-model. We demonstrate algorithmic completeness of Visa language parallel programming at the level of a parallel program scheme. Mating parallel scheme programming with its nodes interpretation programming in conventional programming languages and adjustable granularity of for MPSoC parallel computations are discussed. Finally, architecture challenges for MPSoC parallel programming support are discussed.
  • Design Challenges: Stitching and Debugging Multi Processor solutions on FPGA's
    Yankin Tanurhan, Sr. Director, Applications and IP Solutions, Actel Corporation, USA
Session 11: Core Based Design Environments
  • MeP (Media Embedded Processor), a configurable and extensible microprocessor designed for heterogeneous multi-processor SoC
    Masataka Matsui, Senior Manager, Digital Media SoC (System-on-a-Chip) Dept., SoC Research & Development Center, Toshiba Corp., Japan
    MeP, a 32-bit configurable embedded microprocessor, is integrated on a various MPSoC's such as a single-chip HD DTV decoder, an automotive image recognition LSI and a mobile video-application processor. In these SoC's MeP is used with various extensions such as a VLIW audio DSP coprocessor and an MPEG4 video codec hardware engine.
    This talk presents a review of the architecture, tools and co-design flow of MeP with some MPSoC applications, which would show that MeP is by nature developed for heterogeneous MPSoC.
  • Industrial usage of C-based synthesis and verification
    Kazutoshi Wakabayashi, System CAD, System Devices Res. Labs. NEC Corp., Japan
    We present how C-based behavioral synthesis is practically used for various chips. Though C-based behavioral syntheis has been thought as a toy tool, but, several million dollar chip are designed by C-based synthesis in NEC last year. The chips are not only for Data flow type application such as DCT, FEC, encription, but also controll dominated circuits such as DMA controller, bus bridge, timer, seqecenser, CPU. We will introduce our design environment and show some stastical data on design efficiency and simulation efficiency.
  • Synchronous Debugging of Multicore Systems
    Vojin Zivojnovic, VP ESL Tools, Development Systems group, ARM Inc., Irvine CA, USA
Session 12: Application for Core Based Design
  • Multithreaded processors in embedded applications
    Steffen Buch, Infineon Technologies AG, Germany
    Memory access becomes more and more the bottleneck in embedded processor applications. Often deep memory hierachies up to three levels (L1-, L2-cache and main memory) are used to alleviate this effect. Especially large on-chip L2 caches are very expensive and power hungry. Furthermore applications demand higher performance but clock speeds of embedded processors do not increase very quickly beacause of memory access and power issues. One solution, with a big impact on area however, are multi-processor systems. Another way of increasing the effective processor performance with only a modest overhead in terms of area is multi-threading.
    In this talk scenarios for the application of multi-threaded processors in SoC designs are presented and different aspects such as balanced system design and programming models. With an analogy to modern communication systems an idea how to apply multithreading to increase performance of MPSoCs is given. Finally, two examples for multi-threaded processor designs at Infineon are presented.
  • Flexible CPUs for SoC Design
    Trevor Mudge
    , University of Michigan, USA
    This talk will overview flexible CPUs and their use in SOCs. We will examine CPUs that are morphable at run-time, such as those offered by FPGA vendors Xilinx and Altera. We will also examine those that are morphable at design time such as the solutions offered by Tensilica and ARC. We will discuss the cost of flexibility by comparing and contrasting implementations as ASICs, structured ASIC, or an FPGAs. The impact on SOC power will also be discussed.
  • Multiprocessor SoCs: why is it so hard to define and program these architectures ?
    Frédéric Pétrot, TIMA Laboratory, France
    People of the high performance computing field have struggled for years trying to program their highly regular parallel machines in an efficient way to solve numerical problems. The emergence of heterogeneous and ad-hoc MPSoC platforms for consumer applications makes it even worse to define architectures and programming models that exploits at best the hardware and software processing power provided by these platforms.
    The talk reviews hardware level program execution on an MPSoC architecture and pinpoints implementation aspects that are worth considering to meet applications constraints. It also gives a few hints on actual solutions.
  • Communication Platforms for Network-on-Chip
    Hannu Tenhunen, School of Information Technology, Royal Institute of Technology (KTH), Sweden
  • Everything I know about software radio in 10 minutes or less
    Wayne Wolf
    , Princeton University, USA
    Software defined radios and cognitive radios promise more powerful and secure communications by taking advantage of programmable digital systems. However, both the hardware and software for a software-defined radio must be carefully architected, particularly if they are to operate from batteries.  This talk will introduce some basic concepts in software-defined radio and identify some design challenges.
Business Session B1: Design Methods Trends
  • Design of Programmable Platforms: From ASIC to ASIP
    Heinrich Meyr, RWTH Aachen University , Germany and Coware, Inc., San Jose , California
    It now seems clear that complex programmable platforms are becoming the predominate method for delivering system functionality. We argue that future platforms will be heterogeneous multiprocessor systems (MP-SoC). They will contain an increasing number of application specific instruction-set processors (ASIP´s) combined with complex memory hierarchies and on-chip communication networks (NoC). These novel architecture trends promise enormous potential to jointly optimize flexibility and area/energy-efficiency
    In a first part of this talk we discuss the economic and technical rational why ASIP based platforms are a good candidate to built these platforms. In the second part of the talk we discuss the elements of a methodology and the necessary tools to create a successful ASIP (and its interconnect ) as an efficient building block for larger programmable platforms.
  • Parallel Programming Models for Heterogeneous MPSoCs
    Pieter van der Wolf, Philips Research Laboratories, The Netherlands
    We present design technology for the structured design and programming of embedded heterogeneous multi-processor systems.  A key element of the design technology is a task-level interface, named TTL. TTL can be used for developing parallel application models and implementing them as a set of communicating hardware and software tasks on a multiprocessor platform infrastructure. By linking application development and implementation aspects, TTL integrates the specification and design phases in the MPSoC design process. Two design cases demonstrate the efficient implementation of TTL on different architectures. Industry-wide standardization of a task-level interface will facilitate reuse of function-specific hardware / software modules across companies.
  • Security Technologies for SoCs
    Hiroto Yasuura, Director of System LSI Research Center, Kyushu University, Japan
    Application area of SoC has been spread to various social infrastructures handling "Trust" and "Value"  as e-commerce and e-government.  New technologies on security are required in design of SoC, e,g. implementations of security cores for cryptography and hash functions,  protection of programs and data on SoC from attacking, and secure design/fabrication/test flow for SoC. In this talk, new problems and solutions for secure SoC design are presented. As an example of the security technologies, implementation of PID system (Personal ID System) developed by System LSI Research Center of Kyushu University is introduced.
Business Session B2: Business Models for MPSoC


  • Moderator: Richard Goering, Managing editor, EDA, EE Times, USA
  • DFM: Where Design, Lithography and Process Meet
    Raul Camposano, Sr. VP, GM and CTO, Synopsys, USA
    Manufacturing and yield, which used to be the domain of the fabs, are increasingly becoming an issue in all steps of design — from process modeling to synthesis. This is particularly true for technology nodes at 90 nanometers (nm) and below. Yield loss mechanisms, both functional and parametric, have become dependant on the design and not only on the manufacturing process. Yield challenges must be addressed throughout the design flow. This talk addresses the challenges design technology is facing to cope with yield loss mechanisms. The topics include incorporating yield-rated cells and probabilistic methods such as statistical timing analysis to address yield losses early in the design. Routing optimization techniques such as minimizing critical areas for shorts and open circuits, wire-spreading, redundant vias and dummy metal fills improve manufacturability for metal layers. Further down the tool chain, resolution enhancement techniques used in mask synthesis address lithography, improving printability and hence yield. They include OPC, the addition of assist features (AF), the use of phase-shift masks (PSM), and so on. Manufacturing process knowledge is becoming evermore important in design to enable effective yield modeling. TCAD models are making their way into manufacturing, helping for example to simulate statistical variations of electrical parameters as a function of process parameters. In summary, an effective approach to optimize for yield must take into account design, lithography and process.
  • Recent Trends in the Design of Multimedia SoCs
    Santanu Dutta, nVIDIA Corporation, Digital Media Processor Group, USA
    The talk will have three main parts. Part 1 will outline the digital revolution. Part 2 will Focus on the market dynamics. Part 3 will analyze how the digital revolution and the market dynamics together play a role in influencing today's multimedia SoC design trends.
  • SOC Design Foundry
    Youn-Long Steve Lin, National Tsing Hua University & Global Unichip Corp., Taiwan
    I will talk about a new business model called SOC design foundry. This model expands semiconductor wafer foundry's service to electronics system houses which previously have no or very little experience/capability in IC design. A design foundry builds up SOC platform, IP portfolio, and chip implementation methodology so that it enables its system house customers gaining competitive edge by implementing its own differentiators down to the silicon. Challenges encountered will also be discussed.
  • Coo-petition for SoC Process and Design Infrastructure: The Crolles2 Alliance
    Philippe Magarshack, FTM Group Vice-President, Central CAD and Design Solutions GM, STMicroelectronics, France
    While Process integration capabilities continue to follow Moore's Law, the cost to develop and produce state-of-the-art SoCs is increasing at an even faster rate. In order to mitigate these costs, the Crolles2 Alliance partners (Freescale, Philips, ST), have been sharing 300mm CMOS process R&D since 2002.
    The three partners are now sharing even more R&D for SoC infrastructure, starting with cell libraries, design kits, and now non-competitive IP developments, as well as SoC infrastructure standards initiatives. Still the 3 companies are competing on the same market segments in Wireless, Consumer and Automotive. We will shed some light on the delicate business and technical balance involved.
  • Prospects of SDR for Multi-Standard Radios
    Ulrich Ramacher, Infineon Technologies AG, Germany